D. Figueroa, C. Chung, M.D. Cornelius, T. Yew, Yuan-liang Li
{"title":"High performance socket characterization technique for microprocessors","authors":"D. Figueroa, C. Chung, M.D. Cornelius, T. Yew, Yuan-liang Li","doi":"10.1109/EPEP.1999.819208","DOIUrl":null,"url":null,"abstract":"At present, most socket suppliers provide different specifications and measurement data based on their own \"in-house\" characterization set-up, which has resulted in a variety of different data reported. To provide a means for designers to correctly decide on a socket or vendor, a standard specification and standard characterization method are necessary. This standard specification will also correctly represent the physical and electrical behavior of the socket. In this paper, a new socket specification is given. To more accurately estimate the socket parasitics, a new 3D modeling method is proposed. A new measurement technique is defined for precisely extracting a socket's model component values. The measurement technique utilizes a de-embedding process and a unique test fixture to ensure the final parasitic values included only the parasitics of the socket. The difference between modeling and measured socket parasitics is within 10%. This technique has been demonstrated and adopted for all Intel socket suppliers.","PeriodicalId":299335,"journal":{"name":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","volume":"74 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1999-10-25","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"9","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"IEEE 8th Topical Meeting on Electrical Performance of Electronic Packaging (Cat. No.99TH8412)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EPEP.1999.819208","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 9
Abstract
At present, most socket suppliers provide different specifications and measurement data based on their own "in-house" characterization set-up, which has resulted in a variety of different data reported. To provide a means for designers to correctly decide on a socket or vendor, a standard specification and standard characterization method are necessary. This standard specification will also correctly represent the physical and electrical behavior of the socket. In this paper, a new socket specification is given. To more accurately estimate the socket parasitics, a new 3D modeling method is proposed. A new measurement technique is defined for precisely extracting a socket's model component values. The measurement technique utilizes a de-embedding process and a unique test fixture to ensure the final parasitic values included only the parasitics of the socket. The difference between modeling and measured socket parasitics is within 10%. This technique has been demonstrated and adopted for all Intel socket suppliers.