A Novel Low-Complexity Power-Efficient Design of Standard Ternary Logic Gates using CNTFET

Abstract

This paper introduces novel low-complexity and power-efficient designs of standard ternary (ST) logic gates like the standard ternary inverter (STI), NAND (STNAND), NOR (STNOR), and XOR (STXOR) gates, along with the ternary minimum (TMIN) and ternary maximum (TMAX) operators using the CNTFET. The proposed designs use pass transistor logic (PTL), which reduces the complexity and increases the power efficiency of the designs. The proposed circuits are simulated in Synopsys HSPICE simulation tool using 32 nm CNTFET model provided by Stanford University. In each case, average power values and propagation delays are duly noted and power-delay-product (PDP) values are calculated. Simulation results prove that the proposed designs are more power-efficient and energy-efficient than the existing designs.