FPGA implementation of a multicasting crossbar switch

G. Jan, S. Leu, W. Liou, Shu I Chen
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引用次数: 1

Abstract

Multicast switches have become indispensible for modern computer networks due to the proliferation of multicast traffic on the Internet. One important issue which greatly affects the performance of a multicast switch is how to reduce data loss caused by blocking during the process of duplication and routing of the packets. This paper proposes a multicast crossbar switch with an inner queue at each cross point. With the proposed architecture, no additional control circuits are needed for performing duplication and self-routing. To reduce data loss, duplicated packets are first stored in the inner queues, then continue to transmit at the beginning of the next time slot. By controlling the interarrival time of two sequential groups of packets, our approach can reduce the rate of data loss to 10−6 or less. Due to simplicity of the proposed architecture, hardware implementation can be realized with ease while delivering good scalability and stackability. The proposed multicast switch has been implemented and verified on an Altera Stratix II EP2S60F1020 chip. It operates at a clock rate of 80 MHz and uses only eight percent of the available look-up tables.
用FPGA实现的一种多播交叉开关
由于Internet上多播流量的激增,多播交换机已成为现代计算机网络中不可或缺的一部分。如何减少分组在复制和路由过程中因阻塞而造成的数据丢失是影响组播交换机性能的一个重要问题。提出了一种在每个交叉点都有一个内部队列的组播交叉交换机。利用所提出的架构,不需要额外的控制电路来执行复制和自路由。为了减少数据丢失,重复的数据包首先存储在内部队列中,然后在下一个时隙开始时继续传输。通过控制两个连续分组的间隔到达时间,我们的方法可以将数据损失率降低到10−6或更低。由于所提出的架构简单,硬件实现可以轻松实现,同时提供良好的可扩展性和可堆叠性。所提出的组播交换机已在Altera Stratix II EP2S60F1020芯片上实现并验证。它以80mhz的时钟速率运行,只使用了8%的可用查找表。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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