A 0.5 μm BiCMOS channelless gate array

Abstract

A BiCMOS channelless gate array using 0.5-μm BiCMOS technology is described. To improve the speed and density of the gate array, a novel feedback-type BiCMOS circuit and the channelless architecture were adopted. The plane-type gate array has 54 K cells and can construct a three-input NAND or NOR gate using one of them. The array realizes the high utilization ratio of basic cells using a four-metal-layer wiring technique. If macrocells are used, the density of the chip becomes more than twice that of a plane-type gate array. The gate delay time of 220 ps was simulated using a feedback-type BiCMOS two-input NAND circuit and 0.5-μm BiCMOS devices with a 4-V power supply. This high-performance BiCMOS channelless gate array can be applied to high-speed computers