The effect of elevated temperature on digital single event transient pulse widths in a bulk CMOS technology

Abstract

Combinational logic soft errors are expected to be the dominant reliability issue for advanced technologies. One of the major factors affecting the soft-error rates is single-event transient (SET) pulse widths. The SET pulse widths, which are controlled by drift, diffusion, and parasitic bipolar transistor parameters, are a strong function of operating temperature. In this work, heavy-ion induced SET pulse widths are reported at temperatures ranging from 25° to 100° C with an autonomous SET capture circuit. Experimental and simulation results in a 90nm bulk CMOS technology indicate an increase as high as 37% in average SET pulse width with increasing operating temperature, with some pulses almost 2 ns long at higher temperatures. The increase in the SET pulse width can be explained by the dependence of bipolar amplification on temperature.