Scalable serial-configuration scheme for MTJ/MOS-hybrid variation-resilient VLSI system

Abstract

A new circuit-characteristic configuration scheme of a nonvolatile logic circuit, where magnetic tunnel junction (MTJ) devices are combined with MOS transistors, is proposed for realizing process, voltage, temperature (PVT)-variation-aware VLSI systems. Faulty logic-function results due to PVT variation are detected by monitoring input-output characteristics of each logic-circuit cell, and adjusted by configuring resistance values of MTJ devices embedded into each logic-circuit cell. The resistance values of MTJ devices are programmed in bit-serial manner by the proposed scheme, which can suppress not only area overhead due to incorporating configuration function but also the number of control signals from peripheral circuitry. It results in adding the configuration capability with compact and scalable implementation.