Methodology to Capture Statistical Effect of Process Imperfections on Glitch Suppression in CNFET Circuits and to Improve by Using Approximate Circuits

Abstract

Carbon nanotube field effect transistor (CNFET) technology has shown tremendous potential, and thus extensively studied among the emerging materials-based technologies to replace Si for the post-Si era. However, emerging technologies including CNFET technology suffer from immature, poor process quality, leading to process imperfections, which in turn degrade circuit performance. This paper presents a methodology to evaluate circuit level impact and design solution related with imperfect process. Monte Carlo simulation is applied to consider the statistical nature of the process imperfections. With a specific study on glitch tolerance (important circuit-level performance metric in advanced technology nodes) in CNFET circuits, our simulation framework provides the link between degradation in glitch tolerance with poor process quality. Moreover, we have proposed that approximate circuits can significantly improve glitch tolerance in comparison to precise counterparts, due to lesser nodes, reduced stacked configurations, and reduced number of connections at some nodes because of simpler topologies. With an example of 4-bit adder and 4-bit multiplier circuits, we have demonstrated that approximate circuits are able to lower the glitch vulnerability to an acceptable level, with a tolerable logic error. Moreover, approximate circuits would also relax the requirement on process quality to keep process-induced failures below certain target value.