{"title":"Demonstration of Mos2 Memtransistor with Poly-Si Source/Drain Featuring Tunable Conductance States and Boosted ION","authors":"K. Li, M. K. Huang, Y. H. Wang, Y. Tseng, C. Su","doi":"10.1109/EDTM55494.2023.10103051","DOIUrl":null,"url":null,"abstract":"Memtransistor, a hybrid transistor and memristor, features both semi-conductive and resistive switching properties. We demonstrate that the resistive property in both $\\text{MoS}_{2}$ crossbar memristor and planar memtransistor structures based on highly compatible CMOS process with heavily-doped poly-Si as bottom electrode (BE) and source/drain (S/D), respectively. Low-resistance/ high-resistance state current ratio $(\\mathrm{I}_{\\text{LRS}}/\\mathrm{I}_{\\text{HRS}})$ in memtransitors can be modified by both back gate and S/D electrodes, favoring operation of artificial neural networks. A boosted ION is found after the set process, exhibiting a new manner to acquire high-performance $\\text{MoS}_{2}$ devices. Our work presents a novel memtransistor concept based on 2D material device for memory and logic applications.","PeriodicalId":418413,"journal":{"name":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2023-03-07","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2023 7th IEEE Electron Devices Technology & Manufacturing Conference (EDTM)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/EDTM55494.2023.10103051","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Memtransistor, a hybrid transistor and memristor, features both semi-conductive and resistive switching properties. We demonstrate that the resistive property in both $\text{MoS}_{2}$ crossbar memristor and planar memtransistor structures based on highly compatible CMOS process with heavily-doped poly-Si as bottom electrode (BE) and source/drain (S/D), respectively. Low-resistance/ high-resistance state current ratio $(\mathrm{I}_{\text{LRS}}/\mathrm{I}_{\text{HRS}})$ in memtransitors can be modified by both back gate and S/D electrodes, favoring operation of artificial neural networks. A boosted ION is found after the set process, exhibiting a new manner to acquire high-performance $\text{MoS}_{2}$ devices. Our work presents a novel memtransistor concept based on 2D material device for memory and logic applications.