Monolithic Binary Optical Logic Gates With Programmable Optical Routing

Abstract

We describe a switching technology that performs both optical logic and the spatial routing functions in a dynamically reconfgurable manner, which provides the basis for a programmable optical logic architecture. Cascadable arrays of binary optical switches that integrate vertical-cavity surfaceemitting lasers (VCSELs) with heterojunction phototransistors (HPTs) and photothyristors (PNPNs) can perform optical routing, optical logic, and fan-out reconfigurably at high speed. Eficient, non-latching HF'TNCSEL switches as well as latching PNPNNCSEL switches have been used to perform single-stage optical logic functions,1 including AND, OR, INVERT, NAND, NOR, and XOR. Although more complex Boolean functions can be derived by cascading sequential logic gate arrays, the process is difficult and is hardware-intensive. An alternative approach is to design an optical logic gate array that can be reconfigured and thus be used repeatably to perform sequential logic operations using the same hardware. Gate level reconfigurability allows each array to be re-used to perform different logic and routing functions during successive operations. By buffering the optical outputs of the previous stage while the array is reconfgured, a single logic array can perform the entire process sequence. To implement a cascadable, programmable, and thus reusable optical logic gate array, the spatial routing and logic functions must be integrated. For example, a Boolean function can be expressed in the sum of products form, using dual-rail logic inputs and the AND and OR logic functions. This is illustrated for the simple two-input case in Fig. l(a), which shows the routing and logic functions required in the 3-stage min-term generation process. Its optoelectronic implementation is also shown in Fig. l(a), which uses three sequential logic arrays each containing HPTNCSEL binary optical switchc:s2 with shufne routing interconnections. Figure l(b) shows three of the common gate-level operations involved: optical routing, fan-out, and logic. Since all three stages are identical except for the routing paths, they can be implemented using a single array by programming the control voltages to select the active nodes, the routing paths, and the fan-out of each stage. Reconfigurability allows a single programmable optical logic gate array (OPLA) to be used, provided that the optical outputs of the previous stage are buffered by an optical buffer memory array (OMA). The design and layout of the basic 2x2 binary optical logic gate (2 inputs, 2 outputs) are shown in Fig. l(c) and 2(b), respectively. The switch concatenates two nodes, each of which contains a segmented HPT and a VCSEL. Every HPT is connected to two VCSELs (at least one of which is associated with another node), and each VCSEL is likewise connected to two different HPTs. The pairing or interconnection of nodes defines a logc gate as well as the routing paths. Each HPT segment is controlled by a bias voltage (Vi or V2) and is serially connected to a different VCSEL. The optical input data impinges on both HPT segments, and depending on the voltages (Vi. V2), the amplified photourrent is routed alternatively to VCSEL #1 or to VCSEL #2 (0, l), or to both VCSELs, where the data is optically regenerated. Thus alternate routing as well as an optical fan-out of 2 can be achieved. In Fig. 2@), the nodes share the same input and output ports, and routing is controlled by the voltages (V1,V2) and (V2',V1'), which define a large number of rouoing configurations. Since the VCSEL is a thresholding device, and i:s C O M & ~ to two HPTs from different nodes, it thus sums their amplified photocurrents and determines the logic outcome -A.B (A-AND-B) or A+B (A-OR-B), respectively -according to whether the inputs have sufficient intensity to collectively or individually switch on the VCSEL. The control voltages (VI ,V~,V~ ' ,V~ ' ) completely specify the logic and routing functions, and the regenerated logic output can emerge from either VCSEL. In the (l,O,l,O) or the (O,l,O,l) configuration (Fig. 2), a single optical logic output emerges from port A or port B, respectively, for a fan-out of 1. In the (l,l ,l ,l) configuration (Fig. 3), the logic output emerges from both ports for an optical fan-out of 2. Binary logic with and without fan-out are experimentally demonstrated in Fig. :!(a,b) and Fig. 3(a,b), respectively. This provides a flexible technology for a compact, dynamically programmable logic gate array.