Xing Zhang, Ru Huang, X. Xi, M. Chan, P. Ko, Yangyuan Wang
{"title":"The investigation of recessed channel SOI devices","authors":"Xing Zhang, Ru Huang, X. Xi, M. Chan, P. Ko, Yangyuan Wang","doi":"10.1109/ICSICT.1998.786075","DOIUrl":null,"url":null,"abstract":"Recessed channel SOI devices were investigated. In this paper, the structure and processing of such devices is described in detail. The characteristics of a SOI MOSFET using recessed channel technology are much better than normal thick non-depleted and thin-film fully depleted SOI MOSFETs. The 0.15/spl sim/4.0 /spl mu/m recessed channel SOI MOSFETs with a silicon channel film of 70 nm and a source/drain silicon film of 160 nm are developed using a submicron process. The transconductance and drain current are increased by 40% more than thin-film fully depleted SOI MOSFETs.","PeriodicalId":286980,"journal":{"name":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","volume":"9 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"1998-10-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"1998 5th International Conference on Solid-State and Integrated Circuit Technology. Proceedings (Cat. No.98EX105)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICSICT.1998.786075","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
Recessed channel SOI devices were investigated. In this paper, the structure and processing of such devices is described in detail. The characteristics of a SOI MOSFET using recessed channel technology are much better than normal thick non-depleted and thin-film fully depleted SOI MOSFETs. The 0.15/spl sim/4.0 /spl mu/m recessed channel SOI MOSFETs with a silicon channel film of 70 nm and a source/drain silicon film of 160 nm are developed using a submicron process. The transconductance and drain current are increased by 40% more than thin-film fully depleted SOI MOSFETs.