An 8Gbps discrete time linear equalizer in 40nm CMOS technology

Abstract

This paper introduces a new circuit technique for a discrete-time linear equalizer that can be used with current-integrating decision feedback equalizers. The DTLE samples and amplifies the input data in a clock phase then holds the output data in the other clock phase. The latter is the integrating phase of a current-integrating DFE. The DTLE is designed for a half-rate 8-Gbps serial-link receiver equalizer in 40-nm CMOS technology and draws 190-uW from a 1.1-V supply. The technique uses clocked current sources improving the power consumption.