ASIC Implementation of Low Power Decimation Filter for UMTS and GSM Sigma-Delta A/D Converter

Abstract

This work proposes an ASIC implementation of low power non-recursive decimation filters in a GSM and UMTS dual mode sigma delta ADC. An alternative that saves 70% to 80% power consumption to the standard CIC approach is discussed here with a decimation factor of m-th power of two and m-th power of three. More research is done to find the break-even point between power consumption and silicon area for non-recursive and recursive architectures. The chip is fabricated in 0.35 mum CMOS and consumes 4.72 mW in GSM and 5.54 mW in UMTS mode, both at Vdd=2.5 V.