Technology and Optimizations for the NOI-Nano-Triode

Abstract

This paper adds some contributions for a Nothing On Insulator (NOI) nano-triode. The concept was introduced first time in 2018. The NOI-nano-triode has the advantages as: reduced sizes as a NOI transistor, a seriously improved subthreshold slope from 650/dec of an experimental vacuum transistor to 210mV/dec of the simulated NOI-nano-triode. The paid price is a non-null gate current. Besides to the optimal architecture with minimum SS parameter, the paper presents a technological flow for this device, aided by Athena tool.