Mixed Mode Circuit Simulation of a Junction-Less Transistor and a Comparative Study with CMOS Inverter

Abstract

Dual Gate Enhancement Mode Junction Field Effect Transistor (DG-JFET) are recognized as one of the possible choice to continue the scaling beyond the conventional limits. In this work, from device perspective, characteristics and inverter characteristics of DG-JFETs and Metal Oxide Semiconductor Field Effect Transistors(MOSFETs) are studied using mixed-mode simulations. The circuit simulation results show that enhancement mode DG-JFET inverters offer excellent ON/OFF performance and better noise margin at a power supply voltage of 0.65 V a requirement for ultra low voltage applications.