Reconfigurable Dynamic Scheduling In Superscalar Processor for FIR Filter

Abstract

A typical superscalar processor fetches, decodes and executes several instructions. The incoming instruction stream is then analyzed for data dependencies and resource dependencies. Instructions are distributed to functional units based on availability of functional unit and data by the dispatcher. This is referred as dynamic instruction scheduling. This paper proposes a dynamic scheduling for the superscalar processor that consists of four functional units, instruction analyzer window of 8 instructions, instruction decoder and dispatcher with register bank. Four independent out of order instructions are executed in parallel. To improve the performance of the processor in terms of speed Tomasulo algorithm is implemented using Isim simulator in Xilinx 14.5 version. To demonstrate potential of the architecture, FIR filter is implemented and compared in terms of execution time with and without dynamic scheduling and also with respect to scalar processor architecture.