FPGA-Based Digital Down Converter for GSM Application

Abstract

The demand for digital down converter (DDC) is the cornerstone technology in software radio standard, which converts the frequency translation, especially in down-converted complex output. This paper briefs design and implementation of reconfigurable DDC that can process input bandwidth about 70MHz to 270 KHz to meet the specifications of Global System for Mobile (GSM) receiver. The proposed design consists of COordinate Rotation Digital Computer (CORDIC) processor and multi-rate decimation filters. By using CORDIC processor the design has achieved maximum spurious-free dynamic range (SFDR). Moreover, implementation of multi-rate decimation filter requires small hardware resources and improves the performance of the DDC design. The proposed DDC has been designed and tested on Xilinx Kintex-7 field programmable gate array (FPGA) board. The advantages of using this flexible DDC can produce a specific output. Experimental results show that the proposed DDC is operated on high processing speed with optimum area to provide cost effective solution in mobile application.