A CMOS low-voltage, high-gain op-amp

Abstract

A CMOS, self-biasing, single-supply op amp is presented. It is designed with regulated cascode transistors for gain enhancement and a common-mode feedback technique for bias stabilisation of complementary regulated cascodes. It enables supply voltage lowering to about 2|V/sub /spl tau//|+2|V/sub ds,sat/| with the maintain of high-gain operation. At V/sub dd/=1.8 V, the measured DC gain of the op-amp is 115 dB, with a unity-gain frequency of 8.6 MHz for a capacitive load of 20 pF.