Analyses and design of low power clock generators for RFID TAGs

Abstract

This paper introduces a new clock generation concept with a PLL for HF RFID systems. Low power consumption of 1.9 muW and a good decoupling against power supply and bias variations are necessary to reach HF RFID timing and energy performance requirements. All presented oscillator topologies can be used in UHF EPCglobal class1 gen2 RFID systems as local oscillator with a minimum frequency of 1.92 MHz. For all oscillators the PSR, power consumption and temperature drift are simulated and partly measured. In the CTS1 project a new VCO and local oscillator concept was developed and manufactured on an Infineon 120 nm CMOS test-chip. The PLL is simulated with the same process technology.