FPGA implementation of space-time encoders

G.N.D. Fadera, L.R.T. Ignacio, M.B.R. Nastor, P. Urriza, J. Marciano
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引用次数: 1

Abstract

This paper describes the concept, architecture, development and demonstration of a 4-transmitter, real-time space-time encoder for multiple-input and multiple-output (MIMO) wireless systems. It is implemented on an FPGA chip in the Altera Stratix EP1S25 DSP Development Kit using VHDL. The system can be configured to use either space-time block coding (STBC) or space-time trellis coding (STTC). It also allows for the use of OFDM to provide frequency diversity and can be reconfigured to use different space-time coding schemes and different modulation schemes including QPSK, 16QAM, and 8PSK. The performance of the different configurations are measured and compared in terms of FPGA utilizations and maximum achievable bit-rate.
空时编码器的FPGA实现
本文介绍了一种用于多输入多输出(MIMO)无线系统的4发射机、实时时空编码器的概念、结构、开发和演示。在Altera Stratix EP1S25 DSP开发套件中,采用VHDL在FPGA芯片上实现。系统可以配置为使用空时块编码(STBC)或空时网格编码(STTC)。它还允许使用OFDM来提供频率分集,并且可以重新配置以使用不同的时空编码方案和不同的调制方案,包括QPSK, 16QAM和8PSK。根据FPGA利用率和最大可实现比特率对不同配置的性能进行了测量和比较。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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