Characteristics of 0.1 /spl mu/m Si MOSFETs with ISRC (Inverted-Sidewall Recessed-Channel) structure for reduced short channel effect

Abstract

To solve the problems of trade-off between the short channel effect and the performance enhancement of sub-quarter-micrometer MOSFETs, we have fabricated a 0.1 /spl mu/m recessed channel MOSFET structure called ISRC (Inverted-Sidewall Recessed-Channel) and verified its superiority. The oxide thickness is 4 nm and the effective channel length is 0.1 /spl mu/m. The maximum transconductance at V/sub D/=2.0 V is 455 mS/mm for nMOSFET and 191 mS/mm for pMOSFET. The DIBL (Drain Induced Barrier Lowering) is kept within 70 mV from V/sub D/=0.1 V to V/sub D/=2.0 V for both devices. By the comparison with the conventional MOSFET, the reduction of short channel effects is demonstrated. By simulation, it is verified that this results from the laterally non-uniformly doped channel profile.