A 200 µA duty-cycled PLL for wireless sensor nodes

S. Drago, D. Leenaerts, B. Nauta, F. Sebastiano, K. Makinwa, L. Breems
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引用次数: 4

Abstract

A duty-cycled PLL operating in burst mode is presented. It is an essential building block of a moderately accurate low-power frequency synthesizer suitable for use in nodes for Wireless Sensor Networks. Once in lock, the PLL's frequency error is less than 0.1% (rms). Fabricated in a baseline 65 nm CMOS process, the PLL occupies 0.19X0.15 mm2 and draws 200 µA from a 1.3-V supply when generating a 1 GHz signal with a duty cycle of 10%.
用于无线传感器节点的200µA占空环锁相环
提出了一种工作在突发模式下的占空环锁相环。它是一个中等精度的低功率频率合成器的重要组成部分,适用于无线传感器网络的节点。一旦锁定,锁相环的频率误差小于0.1% (rms)。PLL采用基准65nm CMOS工艺制造,占地0.19X0.15 mm2,当产生占空比为10%的1ghz信号时,从1.3 v电源中吸取200µa。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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