Strength correlation of power chips by finite element method

Abstract

The ultimate tensile strength of silicon chips can be measured by the three-point bending test. During the test, the breaking load is recorded. The tensile strength of silicon chips can be calculated through the formula between stress and breaking load derived from the beam bending theory. The tests are characterized at die level, which makes it convenient to prepare for the test specimen. However, the dimension of silicon chips may not fall in the range of required geometry, and testing for bigger chip size may have more uncertainty. In this case, the calculated data may over-estimate or under-estimate the strength values. FE modeling technique is used to do correlation with the test data. The 3-D FE model of the silicon chip is created to simulate the three-point bending test. The breaking force taken from the experimental results is applied as the loading condition. The max tensile stress from the simulation results is taken as the tensile strength of the silicon chips. The study of several cases of power chips with different size and thickness is conducted by the experimental three-point bending tests and FE modeling. It is found that in some cases the test results with beam theory and FEA simulation results agree quite well, but in other cases, there is some gap, so correlation of the testing data by the beam theory and by FE modeling is necessary.