D/A conversion: amplitude and time error mapping optimization

Abstract

In this paper, an investigation is made of how the topology dependent amplitude errors and time skews affect the output signal distortion of a digital to analog converter (DAC). The time nonlinearities caused by topology are highlighted as another obstacle that limits the spurious free dynamic range (SFDR). It is shown that proper error mapping can boost up the SFDR in addition to the obtainable static accuracy. A general framework and analysis of the error transfer is given and results of an efficient optimization algorithm are presented.