Simulation study of aging in CMOS binary adders

Abstract

Hot carrier injection (HCI) and negative bias temperature instability (NBTI) become dominant reliability issues in nanometer CMOS technology. These aging effects can induce additional delay which will be accumulated through logic gates and thus degrade the performance of the circuits. This paper discusses performance degradations induced by aging mechanisms in digital integrated circuits. We propose an aging-aware synthesis flow taking into account NBTI and HCI. This flow is demonstrated through the implementation of several architectures of adders using CMOS technology. The simulation results show that Kogge-Stone Adder (KSA) and SKlansky Adder (SKA) are the best solutions whether in terms of the complexity or the resistance to aging effects with induced delay degradation below 0.35%.