Two-Bit Magnitude Comparator Design Using Gate Diffusion Input Technique and Static CMOS Logic

Abstract

Magnitude comparison is an elementary operation of Arithmetic Logic Unit (ALU) of modern processors. Due rapid increased use of portable devices, circuit designs having optimal performance level have become crucial. A novel design of a two-bit magnitude comparator is presented in this paper using Gate Diffusion Input (GDI) technique and Static CMOS (S-CMOS) logic. To determine the performance aspects, the proposed circuit was implemented and simulated in Cadence Virtuoso environment. The proposed work showed 0.212 ns propagation delay and 7.801 uW average power (AP) In order to compare the proposed work, the existing two-bit magnitude comparators were also simulated using Cadence software. 90 nm technology with a supply voltage of 1.0 V have been used in all simulation cases. In accordance to simulation result, the magnitude comparator presented in this paper displayed notable enhancement in all performance aspects.