E. Chen, D. Lottis, A. Driskill-Smith, D. Druist, V. Nikitin, S. Watts, Xueti Tang, D. Apalkov
{"title":"Non-volatile spin-transfer torque RAM (STT-RAM)","authors":"E. Chen, D. Lottis, A. Driskill-Smith, D. Druist, V. Nikitin, S. Watts, Xueti Tang, D. Apalkov","doi":"10.1109/DRC.2010.5551975","DOIUrl":null,"url":null,"abstract":"Non-volatile STT-RAM (spin transfer torque random access memory) is a new memory technology that combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM and the non-volatility of Flash with essentially unlimited endurance. It has excellent write selectivity, excellent scalability beyond the 45 nm technology node, low power consumption, and a simpler architecture and manufacturing process than first-generation, field-switched MRAM. A magnetic tunnel junction (MTJ) device (Fig. 1) is used as the information storage memory element, and its magneto-resistance is used for information read-out. To make the STT-RAM technology competitive with mainstream semiconductor memories, the writing current has to be reduced so that the MTJ can be switched by a minimum sized CMOS transistor. In this paper, we discuss our approaches and results in writing current reduction; device read and write performances; robustness against read disturb switching and barrier break down; and prospects of scaling to future smaller nodes.","PeriodicalId":396875,"journal":{"name":"68th Device Research Conference","volume":"373 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2010-06-21","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"20","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"68th Device Research Conference","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/DRC.2010.5551975","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 20
Abstract
Non-volatile STT-RAM (spin transfer torque random access memory) is a new memory technology that combines the capacity and cost benefits of DRAM, the fast read and write performance of SRAM and the non-volatility of Flash with essentially unlimited endurance. It has excellent write selectivity, excellent scalability beyond the 45 nm technology node, low power consumption, and a simpler architecture and manufacturing process than first-generation, field-switched MRAM. A magnetic tunnel junction (MTJ) device (Fig. 1) is used as the information storage memory element, and its magneto-resistance is used for information read-out. To make the STT-RAM technology competitive with mainstream semiconductor memories, the writing current has to be reduced so that the MTJ can be switched by a minimum sized CMOS transistor. In this paper, we discuss our approaches and results in writing current reduction; device read and write performances; robustness against read disturb switching and barrier break down; and prospects of scaling to future smaller nodes.