Low power in-memory computing based on dual-mode SOT-MRAM

Farhana Parveen, Shaahin Angizi, Zhezhi He, Deliang Fan
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引用次数: 20

Abstract

In this paper, we propose a novel Spin Orbit Torque Magnetic Random Access Memory (SOT-MRAM) array design that could simultaneously work as non-volatile memory and implement a reconfigurable in-memory logic (AND, OR) without add-on logic circuits to memory chip as in traditional logic-in-memory designs. The computed logic output could be simply read out like a normal MRAM bit-cell using the shared memory peripheral circuits. Such intrinsic in-memory logic could be used to process data within memory to greatly reduce power-hungry and long distance data communication in conventional Von-Neumann computing systems. We further employ in-memory data encryption using Advanced Encryption Standard (AES) algorithm as a case study to demonstrate the efficiency of the proposed design. The device to architecture co-simulation results show that the proposed design can achieve 70.15% and 80.87% lower energy consumption compared to CMOS-ASIC and CMOL-AES implementations, respectively. It offers almost similar energy consumption as recent DW-AES implementation, but with 60.65% less area overhead.
基于双模SOT-MRAM的低功耗内存计算
在本文中,我们提出了一种新的自旋轨道转矩磁随机存取存储器(SOT-MRAM)阵列设计,它可以同时作为非易失性存储器和实现可重构的存储器逻辑(and, OR),而无需像传统的逻辑存储器设计那样在存储器芯片上附加逻辑电路。计算的逻辑输出可以像普通的MRAM位单元一样使用共享存储器外围电路简单地读出。这种内在的内存逻辑可以用于在内存中处理数据,从而大大降低传统冯-诺伊曼计算系统的耗电量和长距离数据通信。我们进一步采用使用高级加密标准(AES)算法的内存数据加密作为案例研究,以证明所提出设计的效率。器件与体系结构的联合仿真结果表明,与CMOS-ASIC和CMOL-AES实现相比,该设计的能耗分别降低了70.15%和80.87%。它提供了与最近的DW-AES实现几乎相同的能耗,但面积开销减少了60.65%。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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