Process Development of Fan-Out with Multi-layer RDL for Chiplets Packaging

Abstract

In this paper, the fabrication process flow and results of a High-Density Fan Out Wafer Level Packaging for Chiplets packaging were presented. Fan-out Chiplets package has a 34.2×26.7 mm2 package size, which includes five layers of 2 µm line and space (L/S) redistribution layers (RDLs). The passivation layer includes 2 µm thickness and the diameter of 3um vias. High density and fine pitch RDLs were used to lay out the Advanced Interface Bus (AlB) connection to numerous channels between chiplets and chiplets. Fan-out chiplets packaging using RDL-1st process flow and a laser de-bonding technique. The fan-out chiplets packaging fabrication process and the Chip to wafer (C2W) assembly process were demonstrated.