Front-plane and Back-plane Bias Temperature Instability of 22 nm Gate-last FDSOI MOSFETs

Abstract

In this work, we investigated Bias Temperature Instability under front-plane and back-plane stress based on 22 nm gate-last FDSOI MOSFETs. The front-plane stress, which was twice the operation voltage, was applied to gate under 25 oC and 125 oC, while the back-plane stress, which was under similar electric field of front-plane stress, was applied to back-gate. The DC I-V measurement was carried out after the removal of the stress. For both nMOSFETs and pMOSFETs, the degradation of Id,lin and Id,sat, and the Vth shift were calculated to measure the deterioration of the devices. The results demonstrated that under similar electric field, the degradation caused by back-plane stress was more severe than that of front-plane stress.