Design exploration of inrush current aware controller for nonvolatile processor

Abstract

Leakage power consumption has become a critical limitation in the normally off low-power systems. Power gating provides a promising solution to reduce leakage energy but cannot avoid data loss. Nonvolatile processor has paved the way to achieve zero leakage power while maintaining data. However, nonvolatile processor faces severe inrush current problem when all nonvolatile memories are backed up in parallel. A large inrush current will occur and induce IR drop, which deteriorates the stability of the entire system. This paper proposes a distributed backup control architecture for nonvolatile processors to cope with the inrush current problem. Furthermore, we devise corresponding algorithms to accelerate backup operations under given maximum tolerable current constraints. The proposed techniques are evaluated on a simulation platform and a prototype chip. Experimental results demonstrate up to 26.3% reduction in backup time compared with the sequential backup strategy under the same inrush current constraint.