Topography simulation of BiCS memory hole etching modeled by elementary experiments of SiO2 and Si etching

Abstract

A topography simulation of BiCS memory hole etching is performed. The model parameters are fitted by elementary experiments of Si and SiO2 etching, and BiCS topography simulation is performed without parameter fitting. Our new model describes the experimental topography of BiCS memory hole, including taper angles and undercuts of stacked films. The point of the modeling is that it takes into consideration removal of O-oriented deposition films by reflected ions from tapered SiO2 sidewall.