VLSI Architecture Design for Adder Convolution Neural Network Accelerator

Abstract

Convolution Neural Network (ConvNet) achieved good performance in a variety of image processing tasks. How-ever, a large number of multiplication operations in convolution layers affect mobile device deployment of the ConvNet. Recently, an Adder Convolution Network (AdderNet) was proposed to reduce the multiplication operations of common convolutional neural networks. In this paper, we analyzed differences in calculation processes between the AdderNet and the ConvNet and proposed the VLSI architecture of the AdderNet. In addition to analyzing resource consumption of adder convolutional layers, we also built the whole LeNet neural network with the adder convolutional layers and calculated inference latency. Experiment results showed the proposed VLSI architecture of the AdderNet reduced the latency by 29.26%. Compared with the multiplication convolution layer, the resource consumptions of DSP, Flip-Flop, and LUT for the adder convolution layer were reduced respectively by 6.25%, 0.31%, and 0.86%.