Low-power and high-performance design for cryptosystem using power aware and pipeline techniques

Abstract

It has been a decade since the National Institute of Standards and Technology (NIST) has selected the Rijndael algorithm as the Advanced Encryption Standard (AES). Since then, AES becomes the new block cipher standard of US government. A couple of years ago, with the shift of the technological trend towards the power aware system design, low power AES architectures gain importance over area and performance oriented designs. In this study, we proposed a low power design called power aware technique for cryptosystem to reduce the power consumption while promising to enhance the level of security and achieve the high performance that adapts its self to the applications with real time requirement.