Si dry etching for TSV formation and backside reveal

Abstract

In 3D IC packaging, through silicon via (TSV) technology is being considered as a promising technology, enabling massive and short interconnections between stacked chips, increasing performance and data bandwidth, and reducing signal delay and the power consumption. Currently, dry etch process plays an important role in TSV fabrication. TSVs with diameters ranging from one hundred to ten micrometers are mainly fabricated by deep reactive ion etching (DRIE) technology. Bosch process is used for DRIE process for producing high-aspect ratio TSVs and non-Bosch process is used for TSV reveal process. In Bosch process, the primary steps are silicon isotropic etching and wall passivation in sequential cycles. SF6 is widely used as the main etching gas for the high density of F+ radicals; C4F8 is used in wall passivation as it polymerizes to deposits on walls to form an etch barrier that is sufficiently impervious to side scattered F+ ions but not to direct ions at the bottom of the via. Wall scalloping occurs primarily near the top of the via where scattered ions have wide trajectories and less at greater depths where ion trajectories are more restricted. After completion of the via-middle TSV integration and front-side wafer processing, the wafer is temporarily bonded onto a carrier wafer which could be glass or silicon. Then Si from the backside of the wafer was removed to make contact with the bottom of the TSVs by a mechanical grind followed by a reveal etch, which is a key step for the successful implementation of TSV. The via reveal was required to maintain acceptably low total thickness variation (TTV) to allow subsequent stacking steps.