Successive Approximation AD Converter using kT/q as an Intermediate

Abstract

Conventional Successive Approximation AD converters consist of a clearly distinguishable DA converter, usually based on a R-2R resistor ladder, in a feedback loop for providing the analog counterpart of the SA register content to the input comparator. In successive conversion steps a refining of the SA register estimate of the input voltage is realised. Starting from the MSB the lesser significant bits are determined after setting of the previous bit in the SA register and comparison of the DA converter output with the actual input voltage. The conversion accuracy is largely determined by the matching of precision components in the DA converter. For this reason the properties of a translinear core are usually not taken into consideration. Nevertheless, such a circuit reveals interesting features for reducing the total circuit complexity of the AD converter, which would allow the circuit to be realised in a bipolar process with conservative design rules instead of a CMOS process. This is an interesting property in smart sensors where process compatibilty with the sensor process is essential, whereas only a moderate resolution is required. In the novel approach presented, a translinear core is employed to serve as both the comparator and the DA converter.