A Fault Detection AES Scheme for Resource-Constrained Embedded Systems

Abstract

The fault injection attack is an effective cryptanalysis technique against symmetric and asymmetric encryption algorithms., several countermeasures that detect errors in processing have been proposed in order to protect the Advanced Encryption Standard (AES) against Differential fault analysis (DFA). In this paper, a parity error-detection scheme has been presented in order to secure AES 32-bits embedded systems with resource constraints. This scheme is based on parity comparison between the correct parity of the round output and the predicted parity according to the processing steps of the AES round. The proposed AES hardware scheme was designed and synthesized using the Xilinx Virtex-5 FPGA. The experimental results show that the area overhead and the decreasing time are about 2.5% and 22% respectively. The proposed countermeasure achieves high fault coverage reaching 93 %.