Performance Analysis of 6T SRAM Cell on Planar and FinFET Technology

Abstract

Embedded SRAM cell have become an immanent part in modern SoCs because of the faster memory operation and lower power consumption.As CMOS devices scaling down, there will be a lot of consequences such as short channel effects which will affect the device performance. FinFET technology a technology to overcome the effects of short channel effects by giving better control for gate over the channel and to improve the performance of 6T Static Random Access Memory (SRAM) circuit design. The purpose of this study is to simulate and evaluate the performance of planar and FinFET-based 6T SRAM cell and compare their results. The factors considering in this paper to observe the performance of SRAM are SNM, write margin, read current, leakage and standby leakage.The stability of SRAM bit cell is determined by static noise margin analysis, by butterfly method. Here for all the analysis and simulations Hspice is used in 16nm technology.