Evaluation of epi layer resistivity effects in mixed-signal submicron CMOS integrated circuits

Abstract

This paper illustrates a simple model for calculation and experimental evaluation of epi layer resistance. The model can be used during early stages of mixed-signal integrated circuit design, to estimate the effects of switching noise injection from digital cells to analog circuitry. Moreover, the proposed model leads to a simplified equivalent circuit that can be used for fast SPICE-level simulations of crosstalk effects.