A low power 6-bit current-steering DAC in 0.18-μm CMOS process

Abstract

In our work we are interested in the design of a new architecture of Current-steering DAC Converter a 6bits, operates at 300MHz sampling rate and 1.8V supply voltage, implemented in 0.18um CMOS technology for Ultra-wideband (UWB) transceivers. This work achieves the static differential non-linearity errors (DNL) and integral non linearity errors (INL) are between 0.0583/-0.0600 LSB and 0.0397/-0.1142 LSB, respectively. The spurious free dynamic range (SFDR) at 300-MSPS remains above 60.60dB for input frequency up to 100 MHz. The Total power dissipation is 944.64 uW with 1.8V power supply. The surface of the DAC is 0.006 mm2.