The 1.44F/sup 2/ memory cell technology with the stacked-surrounding gate transistor (S-SGT) DRAM

Abstract

The proposed Stacked-Surrounding Gate Transistor (S-SGT) DRAM is structured by stacking several SGT-type cells in series vertically. When the S-SGT DRAM is stacking 4 cells and one bit-line of both S-SGT and the normal DRAM has 1 K-bit cells, the S-SGT DRAM can realize a cell area per bit of 1.44F/sup 2/, while cell area per bit of the normal DRAM with the same design rule is 12F/sup 2/. Also the S-SGT DRAM achieves a 230% larger signal capacitance over total bit-line capacitance (Cs/Cb) than that of the normal DRAM.