Design and simulation of asynchronous level crossing ADC using feedback DAC

A. Antony, Shobha Rekh Paulson, D. Moni
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引用次数: 1

Abstract

Design and implementation of an asynchronous LC-ADC with feedback DAC in 180nm technology using cadence is presented in this paper. Operating at 110Hz using 0.8 V supply voltage, the ADC achieves 47dB SNDR for 684nW power consumption. This paper also presents a charge sharing 1 bit DAC with pseudo resistors and dummy devices suitable for an asynchronous level crossing ADC.
基于反馈DAC的异步电平交叉ADC的设计与仿真
本文介绍了一种采用cadence技术在180nm工艺下设计并实现的带反馈DAC的异步LC-ADC。该ADC工作频率为110Hz,电源电压为0.8 V,功耗为684nW, SNDR为47dB。本文还提出了一种具有伪电阻和虚拟器件的电荷共享1位DAC,适用于异步电平交叉ADC。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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