{"title":"A novel MASH 2-1 sigma-delta A/D converter with high-to-low conversion for closed-loop MEMS accelerometer interface","authors":"Hongzhe Li, Feng Wu, Meng Zhao, Zhongjian Chen, Wengao Lu, Yacong Zhang","doi":"10.1109/INEC.2016.7589323","DOIUrl":null,"url":null,"abstract":"In this paper, an A/D converter offering the high-to-low level shifter function applied to the high range digital closed-loop MEMS accelerometer interface is presented. In the interface circuit, the analog front-end circuit works in the high-voltage domain and the digital back-end circuit works in the low-voltage domain, however, the cascade MASH 2-1 sigma-delta ADC just can achieve high-voltage signal converting to low-voltage signal without introducing additional high-to-low transition module. The level shifter is mainly realized by the first integrator by means of using switched-capacitor charge transfer principle. The cascade MASH 2-1 sigma-delta ADC performs a maximum signal-to-noise-plus-distortion ratio (S/(N+D)) rms/rms of 113.6 dB with 200 Hz bandwidth and sampling clock of 100-kHz. The interface was designed in TSMC 0.35 um CMOS process and was sent to the foundry to prototype.","PeriodicalId":416565,"journal":{"name":"2016 IEEE International Nanoelectronics Conference (INEC)","volume":"20 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2016-05-09","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2016 IEEE International Nanoelectronics Conference (INEC)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/INEC.2016.7589323","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper, an A/D converter offering the high-to-low level shifter function applied to the high range digital closed-loop MEMS accelerometer interface is presented. In the interface circuit, the analog front-end circuit works in the high-voltage domain and the digital back-end circuit works in the low-voltage domain, however, the cascade MASH 2-1 sigma-delta ADC just can achieve high-voltage signal converting to low-voltage signal without introducing additional high-to-low transition module. The level shifter is mainly realized by the first integrator by means of using switched-capacitor charge transfer principle. The cascade MASH 2-1 sigma-delta ADC performs a maximum signal-to-noise-plus-distortion ratio (S/(N+D)) rms/rms of 113.6 dB with 200 Hz bandwidth and sampling clock of 100-kHz. The interface was designed in TSMC 0.35 um CMOS process and was sent to the foundry to prototype.