Thin-film heterojunction field-effect transistors for ultimate voltage scaling and low-temperature large-area fabrication of active-matrix backplanes

Abstract

Thin-Film heterojunction field-effect transistor (HJFET) devices with crystalline Si (c-Si) channels and gate regions comprised of hydrogenated amorphous silicon (a-Si:H) or organic materials are demonstrated. The HJFET devices are processed at 200°C and room temperature, respectively; and exhibit operation voltages below 1V, subthreshold slopes in the range of 70-100mV/dec and off-currents as low as 25 fA/μm. The HJFET devices are proposed for use in active matrix backplanes comprised of low-temperature poly-Si (LTPS) as the c-Si substrate. Compared to conventional LTPS devices which require process temperatures up to 600°C and complex fabrication steps, the HJFET devices offer lower process temperature, simpler fabrication steps and lower operation voltages without compromising leakage or stability.