{"title":"A 0.75V continuous-time sigma-delta analog-to-digital converter in CMOS technology","authors":"A. Essawy, A. Ismail, M. Dessouky","doi":"10.1109/ICCDCS.2014.7016164","DOIUrl":null,"url":null,"abstract":"In this work, a low-voltage implementation for continuous-time ΣΔ analog-to-digital converters is proposed. The low-voltage implementation technique is based on implementing the sigma delta integrators using CMOS inverters. The proposed technique is applied to a third-order single loop modulator. The first integrator in the loop filter is an active RC integrator, while the remaining integrators are Gm-C based. A 74 dB SNDR is achieved for a signal bandwidth of 41 kHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V supply, in 65 nm CMOS technology.","PeriodicalId":200044,"journal":{"name":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","volume":"24 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2014-04-02","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"0","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2014 International Caribbean Conference on Devices, Circuits and Systems (ICCDCS)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ICCDCS.2014.7016164","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 0
Abstract
In this work, a low-voltage implementation for continuous-time ΣΔ analog-to-digital converters is proposed. The low-voltage implementation technique is based on implementing the sigma delta integrators using CMOS inverters. The proposed technique is applied to a third-order single loop modulator. The first integrator in the loop filter is an active RC integrator, while the remaining integrators are Gm-C based. A 74 dB SNDR is achieved for a signal bandwidth of 41 kHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V supply, in 65 nm CMOS technology.