A 0.75V continuous-time sigma-delta analog-to-digital converter in CMOS technology

A. Essawy, A. Ismail, M. Dessouky
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Abstract

In this work, a low-voltage implementation for continuous-time ΣΔ analog-to-digital converters is proposed. The low-voltage implementation technique is based on implementing the sigma delta integrators using CMOS inverters. The proposed technique is applied to a third-order single loop modulator. The first integrator in the loop filter is an active RC integrator, while the remaining integrators are Gm-C based. A 74 dB SNDR is achieved for a signal bandwidth of 41 kHz and sampling frequency of 100 MHz, while consuming 1 mA from 0.75 V supply, in 65 nm CMOS technology.
CMOS技术中的0.75V连续时间σ - δ模数转换器
在这项工作中,提出了一种用于连续时间ΣΔ模数转换器的低压实现。低压实现技术是基于利用CMOS逆变器实现σ δ积分器。将该方法应用于一个三阶单环调制器。环路滤波器中的第一个积分器是一个有源RC积分器,而其余的积分器是基于Gm-C的。在65 nm CMOS技术中,信号带宽为41 kHz,采样频率为100 MHz,同时消耗0.75 V电源1 mA,实现了74 dB SNDR。
本文章由计算机程序翻译,如有差异,请以英文原文为准。
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