Variable precision, mixed fixed/floating point MAC unit for DNN accelerators

Abstract

Artificial intelligence has become more popular than ever in past few years. Deep neural networks are being used in various use cases e.g., image processing, data analysis and etc. MAC operations are the core of DNNs thus making MAC units a very crucial element of any DNN accelerator. This paper presents a Variable precision, mixed fixed/floating point MAC unit capable of performing single precision floating-point MAC. Also, proposed MAC unit features additional modes for performing one 32-bit fixed-point MAC or two concurrent 16-bit fixed-point MACs or four concurrent 8-bit fixed-point MACs. Aside from high flexibility in number precision, proposed MAC unit uses recurring Karatsuba algorithm to implement higher bit-count multiplication only by using 8-bit multiplier and 8-bit adders. Proposed MAC unit has achieved 44.64 MOPS in 32-bit floating-point, 44.64 MOPS in 32-bit fixed-point, 89.29 MOPS in 16-bit fixed-point and 178.57 MOPS in 8-bit fixed-point on FPGA board ‘NEXYS 4 DDR’ featuring XILINX ‘xc7al00tcsg324-1’ FPGA chip.