Low-power memory repair for high defect densities

Abstract

We illustrate that memory repair for high fault rates can be exploited for improving yield, extending lifetime, reducing power, and improving reliability, and consequently can be used to push aggressively the limits of technology scaling. We also present recent advances in low-area and low-power memory repair for high fault rates. As one of our main goals is to use this repair for reducing as much as possible the power dissipation of the memory system, the power dissipation of the repair circuitry should be kept as low as possible. To comply with this constraint, we also propose a repair approach, which further reduces the power dissipation of the repair circuit.