Thermal Test Chip Design and Performance Considerations

Abstract

Increasing device complexity, greater power densities, ever changing packages, and shorter time-to-market deadlines have combined to make thermal characterization efforts more frenzied than ever. A thermal test chip was designed to assist the thermal engineer in answering critical thermal packaging or material questions. It has a standard heat source with integrated temperature sensors in a format that can handle both wire bond and bump chip configurations in a scaleable array size. This allows a single wafer to supply various array sizes to meet changing requirements. The key requirements for a thermal test chip are: (1) Maximum possible heating area relative to chip size (2) Uniform temperature profile across heating area (3) Low temperature coefficient for heating source (4) Temperature sensor in center of chip (5) Simple-to-use temperature sensor(s) (6) Multiple temperature sensors for a temperature profile across chip surface (7) Kelvin Connections (i.e., 4-wire connections) for improved measurement accuracy (8) Chip size that closely approximates the chip being simulated. This paper will describe a thermal test chip that meets these requirements in the simplest manner possible. Insight into future investigations will also be presented.