Design and implementation of SET-CMOS hybrid half subtractor

Abstract

A hybrid SET-CMOS based half subtractor is presented in this paper. Combination of CMOS and SET technology facilitates new advantageous functionalities. The proposed hybrid SET-CMOS based half subtractor is implemented and simulated using T-SPICE. The simulation results are successfully verified with the truth table for the half subtractor. Two different approaches of SET-CMOS hybrid design is explained in this paper. Two main parts of the circuit is formed with the Single electron transistor based network and MOS transistor based network. The circuit of the half subtractor designed using both the approaches is presented in this paper. The stability analysis of the designed circuit is also explained in this paper with the stability plot. Also a performance comparison is given to justify the proposed work.