AIDA-PEx: Accurate parasitic extraction for layout-aware analog integrated circuit sizing

Abstract

This paper presents a new parasitic extractor (PEx) embedded in an automatic layout-aware IC synthesis tool, AIDA, and has the main goal of providing accurate parasitic estimates to lead and accelerate the layout/parasitic-aware optimization of the circuit. Finding a circuit sizing solution that fulfills all specifications after circuit layout is a time-consuming task that requires non-systematic iterations between electrical and physical design steps, which increases the design time of analog integrated circuits (ICs). The performance of automatic layout-aware IC sizing methodologies is heavily dependent on the promptitude of the iterations. The in-loop circuit evaluation encompasses three main steps: circuit simulation, layout generation and parasitic extraction. The proposed approach, unlike previous approaches, it estimates the parasitic capacitances and resistances from a simplified layout that include the floorplan and a non-detailed routing, using an empirical method supported by the data from the process design kit (PDK) files. Experimental results are presented for the UMC 0.13μm process and compared with the industry standard Mentor Graphics' Calibre®.