{"title":"3D IC cooling mechanism by using signaling vias","authors":"A. Gevorgyan","doi":"10.1109/ELNANO.2013.6552044","DOIUrl":null,"url":null,"abstract":"In this paper is discussed the problem of efficient thermal energy removal in 3D integrated circuits (IC) based on thermal via insertion in parallel with using existing signaling vias. This method allows to minimize the number of additional thermal vias and by this save useful area of chip.","PeriodicalId":443634,"journal":{"name":"2013 IEEE XXXIII International Scientific Conference Electronics and Nanotechnology (ELNANO)","volume":"81 1","pages":"0"},"PeriodicalIF":0.0000,"publicationDate":"2013-04-16","publicationTypes":"Journal Article","fieldsOfStudy":null,"isOpenAccess":false,"openAccessPdf":"","citationCount":"1","resultStr":null,"platform":"Semanticscholar","paperid":null,"PeriodicalName":"2013 IEEE XXXIII International Scientific Conference Electronics and Nanotechnology (ELNANO)","FirstCategoryId":"1085","ListUrlMain":"https://doi.org/10.1109/ELNANO.2013.6552044","RegionNum":0,"RegionCategory":null,"ArticlePicture":[],"TitleCN":null,"AbstractTextCN":null,"PMCID":null,"EPubDate":"","PubModel":"","JCR":"","JCRName":"","Score":null,"Total":0}
引用次数: 1
Abstract
In this paper is discussed the problem of efficient thermal energy removal in 3D integrated circuits (IC) based on thermal via insertion in parallel with using existing signaling vias. This method allows to minimize the number of additional thermal vias and by this save useful area of chip.